1. Field of the Invention
The present invention relates to a flat display such as a plasma display or an electroluminescent (EL) display. More particularly, this invention is concerned with an address current suppressing units for use in a brightness drive performed in a flat display.
2. Description of the Related Art
Flat displays including a plasma display and an electroluminescent (EL) display have small depths. Moreover, the flat displays permit the construction of large display screens. The application range and production scale of the flat displays are therefore rapidly expanding.
In general, a flat display utilizes a charge accumulated between electrodes and causes a discharge to emit light for display. For better understanding of the general principle of display, the structure and operation of, for example, a plasma display will be described briefly.
Well-known conventional plasma displays (AC type PDP) fall into one of a dual-electrode type that uses two electrodes for selective discharge (addressing discharge) and sustaining discharge and a triple-electrode type that uses three electrodes for addressing discharge.
In a plasma panel display (PDP) for a color display, infrared rays resulting from discharge are used to excite phosphors disposed in the discharge cells. The phosphors are susceptible to the impact of ions or positive charges induced by the discharge. The above dual-electrode type has a structure such that the phosphors are directly hit by the ions. This structure may reduce the service lives of phosphors.
To avoid the deterioration, the color plasma display usually employs the triple-electrode structure based on surface discharge.
The triple-electrode type falls into an arrangement in which the third electrode is formed on the substrate on which first and second electrodes thereof, used for sustaining discharge, are arranged and an arrangement in which a third electrode is formed on another substrate opposed to the one on which the first and second electrodes are arranged.
In the arrangement in which three electrodes are formed on the same substrate, the third electrode may be placed on, or under, the two electrodes for sustaining discharge.
Furthermore, visible light emitted from phosphors may be transmitted or reflected by the phosphors for observation.
The foregoing plasma displays of different types have the same operating principle. Mention will therefore be made of a flat display in which first and second electrodes for sustaining discharges are formed on a first substrate and a third electrode is formed on a second substrate opposed to the first substrate, by presenting embodiments thereof.
FIG. 6 is a schematic plan view showing a configuration of the aforesaid triple-electrode type plasma display panel (PDP). FIG. 7 is a schematic sectional view of one of discharge cells 10 formed in the plasma display shown in FIG. 6.
As apparent from FIGS. 6 and 7, the plasma display comprises two glass substrates 12 and 13. The first substrate 13 has first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15. The first electrodes 14 and second electrodes 15 serve as sustaining electrodes, lie in parallel with one another, and are shielded with a dielectric layer 18.
A coat 21 (i.e., a coating or layer) made of magnesium oxide (MgO) is formed as a protective coat over the discharge surface that is the dielectric layer 18.
On the surface of the second substrate 12, opposed to the first glass substrate 13, electrodes 16 acting as third electrodes or address electrodes are formed to intersect the sustaining electrodes 14 and 15.
On the address electrodes 16, phosphors 19 each having one of red, green, and blue light-emitting characteristics are placed in discharge spaces 20 each defined by walls 17 formed on the surface of the second substrate 12 on which the address electrodes are arranged.
Discharge cells 10 in the plasma display are separated from one another by partitions.
In the plasma display of the aforesaid example, the first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15 are lying in parallel with one another and paired. The second electrodes (Y electrodes) 15 are driven independently, while the first electrodes (X electrodes) 14 act as a common electrode and are driven by a single driver.
FIG. 8 is a schematic block diagram showing peripheral circuits for driving the plasma display shown in FIGS. 6 and 7. The address electrodes 16 are connected one by one to an address driver 31. During addressing discharge, the address driver 31 applies an address pulse to each address electrode.
The Y electrodes 15 are connected one by one to a Y-electrode scan driver 34.
The scan driver 34 is connected to a Y-electrode common driver 33. For addressing discharge, pulses are generated by the scan driver 34. For sustaining discharge, pulses are generated by the Y-electrode common driver 33, and then applied to the Y electrodes 15 via the Y-electrode scan driver 34.
The X electrodes 14 are connected in common with respect to all display lines on a panel of the flat display.
An X-electrode common driver 32 generates a write pulse and a sustaining pulse, and applies these pulses to the X electrodes 14 concurrently. These drivers are controlled by a control circuit 35. The control circuit is controlled with a synchronizing signal and a display data signal which are supplied by an external unit.
As is apparent from FIG. 8, the address driver 31 is connected to a display data control unit 36 incorporated in the control circuit 35. The display data control unit 36 inputs a dot clock signal CLOCK and a display data signal DATA, which are display data and are supplied from an external unit, and outputs data via, for example, a frame memory 37 incorporated in the display data control unit 36 according to the timing of addressing address electrodes which are to be selected for one frame.
The Y-electrode scan driver 34 is connected to a scan driver control unit 39 in a panel drive control unit 38 incorporated in the control circuit 35. In response to a vertical synchronizing signal V.sub.sync, a signal instructing the start of scanning one frame (or field) and supplied by an external unit, and a horizontal signal H.sub.SYNC that is a signal instructing the start of one horizontal scanning period, the Y-electrode scan driver 34 is driven to select a plurality of Y electrodes 15 in the flat display 30, one by one. Thus, an image of one frame is displayed.
In FIG. 8, Y-DATA denotes scan data that is supplied by the scan driver control unit 39 and used to turn on the Y-electrode scan driver 34 bit by bit. Y-CLOCK denotes a transfer clock pulse for use in turning on the Y-electrode scan driver 34 bit by bit.
Y-STB1 denotes a timing signal for use in turning on the Y-electrode scan driver 34. Y-STB2 denotes a timing signal for use in turning off the Y-electrode scan driver 34.
The X-electrode common driver 32 and Y-electrode common driver 33 in this example are connected to a common driver control unit 40 incorporated in the control circuit 35. The X electrodes 14 and Y electrodes 15 are driven all together (i.e., in common) by reversing polarities of applied voltages alternately. Thus, the aforesaid sustaining discharge is executed.
In FIG. 8, an X-UD signal, supplied by the common driver control unit 40, is used to control the on and off states of the X common driver 32, and the X-UD signal includes voltage signals Vs and Vw. An X-DD signal, supplied by the common driver control unit 40, is used to control the on and off states of the X-electrode common driver and the X-DD signal includes a GND level signal.
Likewise, a Y-UD signal supplied by the common driver control unit 40 is used to control the on and off states of the Y-electrode common driver, and the Y-UD signal includes voltage signals Vs and Vw. A Y-DD signal supplied by the common driver control unit 40 is used to control the on and off states of the Y-electrode common driver and the Y-DD signal includes a GND level signal.
FIG. 9 shows waveforms in a first example of a conventional method of driving the plasma display PDP shown in FIGS. 6 and 7. FIG. 9 shows one drive cycle in a line-sequential drive and self-erasure addressing mode.
In this example, at a time instant (1) during one drive cycle, the voltages of the X electrodes are held at 0V, and a voltage -Vs is applied simultaneously to the Y electrodes associated with all sub-frames constituting one frame. Thus, the voltage wave forms of all the display lines corresponding to the sub-frames are re-shaped in terms of phase.
Since it is unknown which phase was set last for display lines corresponding to sub-frames in a previous frame, the respective of phase all display lines should preferably be synchronized to each other to form a new frame. That is why the operation at the time instant (1) is necessary.
Next, at a time instant (2) in FIG. 9, voltage -Vs is applied to the Y electrodes associated with a display line (C) which is selected by the Y-electrode scan driver and common driver to write display data, while 0V is applied to the Y electrodes associated with the other display lines (D) except the selected display line. (A voltage Vs is a sustaining voltage.)
In this embodiment, a write voltage Vw is applied as a write pulse to the X electrodes at the same time. At this instant, a voltage exceeding a discharge start voltage Vf is applied to the discharge spaces 20. This causes a discharge to start. The selected display line has a voltage Vs+Vw, while the unselected display lines have the voltage Vw.
When Vs+Vw&gt;Vf (discharge start voltage)&gt;Vw is established, a selected display line alone can be discharged.
At the time instant (2), all the cells 10 associated with the selected line are written.
A positive surface charge accumulated between the walls (referred to as "wall charge") is therefore accumulated in the protective coat (MgO coat) over the X electrodes 14 associated with the selected line (C), while a negative wall charge is accumulated in the protective coat (MgO coat) over the Y electrodes associated with the selected line.
As discharge progresses, the wall charges have a polarity causing the electric fields in the discharge spaces 20 to shrink. The discharge therefore dies down and lasts only for one to several microseconds.
Next, at a time instant (4) in FIG. 9, the sustaining pulse of the voltage -Vs is applied alternately to the X electrodes 14 and the Y electrodes 15 associated with the selected display line. The wall charge accumulated is added to the applied voltages. Thus, sustaining discharge is repeated in all the cells except those not to be lit (illuminated).
In this embodiment, at a time instant (3) in FIG. 9, a sustaining pulse is applied to the X electrodes in the cells 10 not to be lit. After a negative wall charge is accumulated in the MgO coat over the Y electrodes associated with the selected line, synchronously with the sustaining pulse applied first to the Y electrodes associated with the selected line, an address pulse ADP of a positive voltage Va is applied selectively to the address electrodes in the cells 10 not to be lit.
Sustaining discharge occurs in all the cells associated with the selected display line. In the cells whose address electrodes are supplied with the address pulse ADP, especially, the sustaining discharges triggers discharge between the address electrodes and Y electrodes. Consequently, positive wall charge is accumulated excessively in the MgO coat over the Y electrodes.
When the voltage Va is set to such a value that allows the produced wall charge itself to exceed the discharge start voltage, after an external voltage is removed, that is, after the X and Y electrodes are set to 0V and the address electrodes are set to ground, the voltage of the wall charge itself starts discharging.
As for this discharge, since the potential difference between the X and Y electrodes is 0V, the space charge or wall charge resulting from the discharge will not accumulate in the MgO coat over the X and Y electrodes. The space charge is recombined and neutralized in the discharge spaces. This action is referred to as self-erasure discharge.
Thereafter, even if the sustaining pulse -Vs is applied alternately to the X and Y electrodes, sustaining discharge will not occur but erasure is effected. As for the cells to be lit, the address pulse ADP is not applied to the address electrodes of the cells. Sustaining discharge alone occurs but self-erasure discharge does not. With a sustaining pulse applied thereafter, sustaining discharge is repeated.
As mentioned above, display data is written for a selected display line during one drive cycle. In this embodiment, the writing is executed for each display line.
FIG. 10 is a timing chart for the writing. In FIG. 10, w denotes a drive cycle for writing. S denotes a drive cycle for sustaining discharge alone and s denotes a drive cycle for sustaining discharge for a previous frame (or field).
FIG. 11 shows waveforms in the second example of a conventional method of driving the plasma display panel (PDP) shown in FIGS. 6 and 7. FIG. 11 shows one sub-frame (or sub-field) period SF in a write addressing mode of an addressing/sustaining discharge separated style.
In this example, one sub-frame period SF consists of at least a reset period 61, an addressing period 62, and a sustaining discharge period 63. The reset period 61 is provided to erase data, concerning the sub-frames of a previous frame, immediately before displaying a new image of one frame. During the reset period 61, all the Y electrodes are de-energized, to be at 0V, and a write pulse of a voltage Vw is applied to the X electrodes at the same time.
Thereafter, the Y electrodes are supplied with a voltage Vs and the X electrodes are de-energized, to be at 0V. Sustaining discharge then occurs in all the cells. This leads to execution of whole-screen write, whereby an erasure pulse EP is applied to the X electrodes 14 so that information recorded in all the cells 10 are erased temporarily. This is the reset period 61.
In this example, during the reset period 61, first, all the Y electrodes are de-energized to 0V. At the same time, all the cells associated with all display lines are discharged; that is, the write pulse of the voltage Vw is applied to the X electrodes. The Y electrodes are then supplied the voltage Vs, and the X electrodes are de-energized to have 0V at the same time. Thus, a sustaining discharge is effected in all the cells. Erasure discharge occurs between the X electrodes and Y electrodes, whereby each wall charge disappears (part of the wall charge is neutralized).
The reset period 61 is useful, for placing all the cells in the same state irrespective of whether or not they are lit for a previous sub-frame, and is intended to hold the wall charge, which triggers an address discharge, at a voltage that does not start a discharge as a result of the next pulse.
In this example, the reset period 61 is succeeded by the addressing period 62. During the addressing period 62, addressing discharge is effected line-sequentially so that the cells are turned on or off depending on the display data to be placed in the cells. First, a scan pulse SCP of 0V is applied to the Y electrodes. The address pulse ADP of the voltage Va is applied to the address electrodes in the cells to be subjected to sustaining discharge or to be lit. Thus, the cells to be lit are discharged for writing. This brings about minor discharge, which will not be discerned directly, between the address electrodes and selected Y electrodes. A given amount of charge is then accumulated in the cells 10. Thus, (address) writing for one display line terminates.
The foregoing operation is performed for the other display lines sequentially. New display data are thus written for all the display lines.
Thereafter, during the sustaining discharge period 63, the sustaining pulse of the voltage Vs is applied alternately to the Y electrodes and X electrodes. Thus, sustaining discharge is effected. An image is displayed in units of controlled sub-frames together constituting a complete frame, for each primary color.
In the aforesaid write addressing mode of an addressing/sustaining discharge separated style, a brightness level of a display screen is determined depending on the length of the sustaining discharge period or the number of sustaining pulses.
A brightness level of a pixel in the display screen depends on the number of sustaining discharge cycles performed during the sustaining discharge period 63 for each sub-frame, under the setting conditions for each sub-frame. In short, a brightness level is dependent on the length of the sustaining discharge period.
In principle, the greater the number of sustaining discharge cycles performed during the sustaining discharge period 63, the higher the brightness becomes. Otherwise, the brightness becomes lower.
For determining a brightness level, an optimal one of multiple predetermined sub-frame patterns, of which the numbers of sustaining discharge cycles are different from one another due to different given weights, is selected for each sub-frame, and then a sustaining discharge is executed for the sub-frame. After this operation is executed for all sub-frames of one frame, a brightness level for the frame is determined.
In this example, as shown in FIG. 12, one frame is divided into eight sub-frames SF1 to SF8. The length of the sustaining discharge period 63 is different from sub-frame to sub-frame.
The reset period 61 and addressing period 62 are the same in length among the sub-frames SF1 to SF8. However, the length of the sustaining discharge period 63 differs from sub-frame to sub-frame. For example, the numbers of sustaining discharge cycles for the sub-frames SF1 to SF8 are set to have a relationship of 1:2:4:8:16:32:64:128. By selecting any one or ones of the patterns shown as the sub-frames SF1 to SF8 in FIG. 12 using addresses, the numbers of sustaining discharge cycles for sub-frames in one frame can be changed appropriately.
In this example, brightness can be set to any one of 256 levels.
This example, based on the addressing mode of an addressing/sustaining discharge separated style, is utilized for the display with a large number of scanning lines (corresponding to display lines) or the full-color display with multiple brightness levels. The configuration and operation for this addressing mode are disclosed in, for example, Japanese Unexamined Patent Publication No. 4-195188.
An example of actual time allocation in the aforesaid example will be described below. Assuming that screen rewriting is performed at 60 Hz, it takes 16.6 ms (1/60 Hz) to rewrite one frame. Assuming that the number of sustaining discharge cycles for one frame is 510, the number of sustaining discharge cycles for the sub-frame SF1 is 2, that for the sub-frame SF2 is 4, that for the sub-frame SF3 is 8, that for the sub-frame SF4 is 16, that for the sub-frame SF5 is 32, that for the sub-frame SF6 is 64, that for the sub-frame SF7 is 128, and that for the sub-frame SF8 is 256. Assuming that it takes 8 microseconds to complete a sustaining discharge cycle, 4.08 ms is required to complete all the sustaining discharge cycles for one frame. The remaining 12 milliseconds or so is allocated to eight addressing periods. It takes about 1.5 milliseconds to complete the addressing period for each sub-frame. Assuming that about 50 microseconds is required for the reset period preceding each addressing period, it takes 3 microseconds to complete each addressing cycle for driving a panel having 500 scanning lines.
The addressing mode of an addressing/sustaining discharge separated style is currently the most effective mode for displaying images at different brightness levels, wherein a memory in an AC plasma display PDP or an electroluminescent (EL) display is utilized for effective use of time.
Address current flowing through an AC plasma display PDP or electroluminescent (EL) display having the aforesaid configuration is broadly divided into address electrode-to-address electrode capacitance discharge current (hereinafter, A-A current), address write current, and address driver loss current.
It is the A-A current that is most dominant in a maximum address current. The A-A current is used to charge or discharge a space having a floating capacitance between address electrodes in a panel.
Referring to FIG. 6, two address electrodes A1 and A2 are adjacent to each other and can therefore be modeled as a capacitance.
A square wave having a voltage expressed below is regarded as a signal to be fed to the address electrode A1: EQU V(t)=VmF(wt)
where, F(wt) denotes a frequency factor of 0 or 1. Assume that the address electrode A2 has a voltage 0 and the capacitance between the address electrodes A1 and A2 is C12, the equation below is established. EQU I(t)=C12Vm F'(wt)
The A-A current is therefore determined by the A-A capacitance, A-A potential difference, and address frequency. The C12 and Vm values are usually unchanged. The peak address current therefore depends directly on the address frequency.
When cells are arranged in a zigzag pattern, the A-A current becomes maximum. To ensure this A-A current, a large power supply is required. The is disadvantageous in terms of cost and installation.
However, since the zigzag pattern is seldom used, a large power supply is not always required.
In a conventional plasma display PDP which cannot control address current actively, a large power circuit is a must.